Scalable VLSI architectures for full-search block matching algorithms
نویسندگان
چکیده
block matching motion estimation (ME) algorithm based on overlapped search data flow. The proposed VLSI architectures have three specific features: (1) they contain a processor element (PE) array which provides sufficient computational power and achieves 100% hardware efficiency; (2) they contain stream memory banks which provide scheduled data flow requested by P E for computing mean absolute distortion (MAD); and (3) they both have minimum memory bandwidth to save 1/0 pin-count. This paper presents two VLSI architectures for full search
منابع مشابه
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplificatio...
متن کاملVLSI architectures for block matching algorithms using systolic arrays
|In this paper, we investigate hardware implementation of block matching algorithms (BMAs) for motion estimation of moving sequences. Using systolic arrays, we propose VLSI architectures for the two-stage BMA and full search (FS) BMA. The two-stage BMA using integral projections reduces greatly computational complexity with its performance comparable to that of the FS BMA. The proposed hardware...
متن کاملCost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms
This paper presents two efficient very large scale integration (VLSI) architectures and buffer size optimization for full-search block matching algorithms. Starting from an overlapped data flow of search area, both systolicand semisystolicarray architectural solutions are derived. By means of exploiting stream memory banks, not only input/output (I/O) bandwidth can be minimized, but also proces...
متن کاملAn Efficient VLSI Architecture for Full-Search Block Matching Algorithms
This paper presents a novel memory-based VLSI architecture for full search block matching algorithms. We propose a semi-systolic array to meet the requirements of high computational complexity, where data communications are handled in two styles: (1) global connections for search data and (2) local connections for partial sum. Data flow is handled by a multiple-port memory bank so that all proc...
متن کاملFast VLSI Implementation for Low Power Motion Estimation Removing Redundant Memory Data Access
| This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously , a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an ineeciently large number of external memory access. Recently, to reduce the number of accesses in one candidate block, a block mat...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1996